The present invention is related to integrated circuit (IC) technology and more particularly related to defect analysis of static random access memory (SRAM) circuits, particularly when such circuits are employed in the characterization of new CMOS manufacturing processes.
With each successive generation of IC technology, the feature sizes become smaller by a factor of approximately 70%. During the development of a new generation of IC technology, it is important to be able to identify and analyze process-induced defects, especially those that cause electrical circuit failures. Corrective measures can then be taken in the developing process to remedy the defects. It is common to use SRAM circuits to do this debugging, since an electrical signal of a defect can be traced to a particular physical location. Historically, the smallest unit of SRAM, a bit cell, consisting of six particular transistors disposed in a small area of the IC wafer surface, is located and physically analyzed by removing successive layers of processed semiconductor material or metalization to look for physical defects. With the advance of technology, the area of the bit cell has become so small that many defects are no longer detectable under a microscope.
Since physical defects are the most easily identified and account for most of the detected failure mechanisms of the process, an analysis of the defective SRAM circuits is instructive. A quantity of wafers (a "lot") are processed using the CMOS process under development. Wafers containing the SRAM circuits are functionally tested and core failure locations (anomalous memory cells)are mapped using software programs previously developed for this purpose. Representative wafers from the lot are selected for analysis based on the defectivity rates or development areas which are of interest. Analysis proceeds with visual inspection of the defective cells using an optical microscope. Suspicious locations are further evaluated using a scanning electron microscope (SEM), if needed. The wafers are then deprocessed using wet chemical or plasma etch sequences to expose successively lower structural levels and another inspection is performed. This cycle continues until all defects have been characterized or the wafer is deprocessed completely to bare silicon. It may also be instructive, along with imaging defects with an SEM, to undertake cursory elemental analysis using Energy Dispersive Spectral Analysis (EDS) to obtain an understanding of the elemental composition of the defects detected.
Typically, a large percentage of failures falls into the category of "non-visible defect" (NVD)--meaning that no defect could be found. If this is a limiting category, a laborious benchtest characterization of like failures in this or other wafers in the lot is undertaken. The electrical defect types can be identified and subsequently analyzed to understand a physical mechanism responsible for the defect. Because of the high labor content required to perform this type of electrical analysis, it is usually only practical to sample failing cells up to the point that there is confidence that a key failure mechanism is identified or understood.
A conventional six-transistor SRAM bit cell 100 is shown in the schematic of FIG. 1. One inverting amplifier consisting of a P-channel MOS transistor 101 and a n N-channel MOS transistor 103 are connected to a second inverting amplifier consisting of P-channel transistor 105 and an N-channel MOS transistor 107 in an input-to-output fashion conventionally known as a latch. Direct current power is supplied VDD to ground, as conventionally shown. An N-channel MOS transistor 109 couples the latch to one bit line BIT and an N-channel MOS transistor 111 couples the latch to a second bit line BIT*, which in normal operation provides binary complement data to data found on the BIT line. The gate of both transistors 109 and 111 are coupled to a word line WL.
It has been shown that defects within such a bit cell can be identified by isolating the bit cell from the power supply, the power supply return (ground), and the remainder of the circuits on the wafer and then supplying controlled power and bias to selected nodes by way of microprobes contacting these nodes at the IC surface. In U.S. Pat. No. 4,835,458, static gate and drain voltage/current characteristics are shown to be measured for selected transistors. Comparisons of characteristics between defective and good transistors can be used to detect the failure mechanism of failed bit cells. As noted before, however, microprobe analysis is a laborious and expensive process for repeated analysis.
Column and row select decoding algorithms have been developed for the particular address space used by the IC; that is, single-bit, four-bit, eight-bit, or the like data groupings. Each column, as shown in FIG. 2, comprises a set of bit cells 100, 100' connected to common BIT and BIT* lines. (The asterisk following a control line is used to designate a complement signal). Single bit cells are accessed by selecting a row (word line WL.sub.1 or word line WL.sub.2, etc.) and appropriate columns. In the "write" mode, the transmission gates 201 and 203 are enabled for the desired columns by WR and WR* lines to the columns and data Dl for the one or more bit cells is written into the bit cell by a write driver 205 found in each column and coupled to the BIT and its complement BIT* lines. "Read" mode allows the data contained in a bit cell to be coupled by way of enabled transmission gates 201 and 203 to one or more sense amps 207 which are usually assigned to each column. In the deselected mode, the BIT and BIT* lines are isolated from the write drivers 205 and the sense amps 207. Further, the BIT and BIT* lines are precharged to a voltage, for example V.sub.DD, by way of transmission gates 209 and 211 to accelerate access time. The transmission gates 209 and 211 are enabled by a precharge PC signal and its complement, PC*, which are generated logically from the conventional read/write and address circuitry.
It has been shown, for example in U.S. Pat. No. 5,034,923, that additional control logic may be added to exercise the BIT and BIT* lines with non-standard combinations of binary logic states over time and the logic state of the BIT or BIT* determined by independent sense amps for the BIT and BIT* lines. In this way, soft defects characteristic of undesired open circuits may be detected from an improper logic level appearing on one of the BIT or BIT* lines. Such detection does not allow characterization of the transistors comprising a latch circuit at other than the defined logic levels. Thus the opportunity for detection and analysis of other process defect mechanisms is missed.
It can be seen, then, that an improvement is needed in an IC design to enable various process defects to be analyzed without laborious microprobing of the circuit and to provide flexibility in the measurement of circuit characteristics.